1. Field of the Invention
The present invention relates to PCI (Peripheral Component Interconnect) Express, and more particularly to a method of compensating for a byte skew of PCI Express and a PCI Express physical layer receiver for the same.
2. Description of the Related Art
PCI Express was introduced in 2002 to overcome speed limitations of conventional PCI, so as to match the speed of current CPUs. The conventional PCI signals were easily distorted due to a parallel transmission interference. Accordingly, it is difficult to increase the clock frequency of a conventional PCI bus. A PCI Express bus, which employs a serial transmission manner, is capable of increasing the clock frequency and is capable of reducing a bus size.
PCI Express, formerly known as 3rd Generation I/O (3GIO), has replaced conventional PCI in a wide variety of fields. PCI Express features low-voltage differential signaling (LVDS), a packet-based data transmission protocol and so on. PCI Express supports a dual simplex type bus. The dual simplex bus includes a pair of one directional data buses, one bus is used for transmitting data and the other bus is used for receiving the data. Due to the LVDS, the PCI Express bus uses a 4-wire interface per lane. As a result, the PCI Express bus uses more wires per data bit than that of the conventional data bus. Also, a message-based protocol and an embedded clocking of the PCI Express bus may contribute to omitting usage of various data control signals required for an interface process of the conventional data bus. The PCI Express bus may include a maximum of 32 lanes. Generally, when a multi-lane bus, such as the PCI Express bus is used, a transmitter transmits divided data to each of the lanes so as to improve transmission efficiency. For example, when the number of the lanes is 4, the data to be transmitted to a receiver is divided to each of 32-bit data packets and the 32-bit data packets are divided to each of 8-bit data packets. Each of the 8-bit data packets is transmitted through each of the four lanes at the same time. The receiver aligns the received data through the wire by compensating for a bit skew between the received data using a comma symbol, and then, aligns the first aligned received data for which the bit skew is compensated, by compensating for a byte skew between the first aligned received data. The bit skew compensation deals with the skew within 8 bits between the received data through each of the lanes bit by bit. Because each of the lanes has a different transmission delay in multi-lane systems, the skew occurs between the lanes. When a transmission speed is relatively low, the skew between the lanes occurs within 8 bits. Accordingly, data reception is effectively performed by compensating for only the bit skew between the lanes. However, in high-speed data transmission devices such as the PCI Express bus, a difference of the transmission delay between the lanes may occur out of the 8-bit range. Accordingly, the high-speed data transmission devices such as the PCI Express bus require a byte skew compensation, as well as the bit skew compensation. The byte skew compensation deals with the byte skew between the received data through each of the lanes byte by byte.
FIG. 1 is a block diagram illustrating a data transmission of a conventional PCI Express bus.
Referring to FIG. 1, the PCI Express bus transmits data using four lanes LANE 0 through LANE 3. A transmitter of the PCI Express bus divides 32-bit data 110 into four 8-bit data 111, 112, 113 and 114. Then, the transmitter transmits the four-data 111, 112, 113 and 114 through each of the lanes LANE 0, LANE 1, LANE 2 and LANE 3, respectively. Each of the four 8-bit data 111, 112, 113 and 114 is transmitted to a wire through an 8-bit/10-bit encoder (not shown) and a serializer (not shown) bit by bit. Other 32-bit data 120, 130, 140, 150 and 160 are respectively divided into four 8-bit data. Then, the divided four 8-bit data are transmitted through each of the lanes. Each of the lanes includes differential wires for transmission and reception, and thus, may include a total of 4 wires.
As shown in FIG. 1, when data are transmitted through each of the four lanes, each of the four lanes takes a different transmission delay from one another. Accordingly, the data transmitted from the transmitter are not simultaneously received by a PCI Express receiver. Therefore, the receiver should eliminate the skew between the received data through each of the four lanes.
FIG. 2 is a block diagram illustrating a data reception of a conventional PCI Express bus.
Referring to FIG. 2, the PCI Express receiver decodes bit data received through the wire using a de-serializer (not shown) to 8-bit data. As shown in FIG. 2, the bit skew and the byte skew occur between the lanes of the received 8-bit data 211, 212, 213, 214, 221, 222, 223, 224, 231, 232, 233, 234, 241, 242, 243 and 244. The reason for the bit skew and the byte skew occurring is that each of the lanes takes a differential transmission delay from one another. The PCI Express bus compensates for the bit skew between the received 8-bit data using a comma symbol to align the received 8-bit data and generates the aligned 8-bit data 271, 272, 273, 274, 275, 276, 277 and 278. The comma symbol may include a particular bit composition. The PCI Express bus generates 32-bit data 280 using the four 8-bit data 271, 272, 273 and 274. Each of the 8-bit data 271, 272, 273 and 274 included in the 32-bit data 280 does not include the bit skew, but the 32-bit data 280 includes the byte skew. Consequently, the PCI Express bus requires a de-skew block 290 capable of compensating for the byte skew between the received 32-bit data and capable of generating 32-bit data 260 having no byte skew.
The conventional de-skew block 290 shown in FIG. 2 compensates for the byte skew using the comma symbol. A conventional method of compensating for the byte skew includes a step of detecting the comma symbol included in the received data, a step of waiting until the comma symbols are detected in all of the lanes, and a step of aligning the received data by delaying the received data through other lanes based on a timing as to when the last comma symbol is detected. However, the conventional method of compensating for the byte skew using only the comma symbol may not appropriately compensate for the byte skew between the received data through each of the lanes, since skip symbols SKP are periodically transmitted after the comma symbol thereby varying each of the alignment points of the received data.
The PCI Express receiver includes an elastic buffer. The elastic buffer may remove the skip symbols included in the received data to prevent an overflow of the buffer when quantity of the received data through a certain lane is large. In addition, the elastic buffer may add the skip symbols to the received data to prevent an underflow of the buffer when quantity of the received data through a certain lane is small. When the addition or the removal of the skip symbol occurs, it is required that the byte skew compensation be performed by reflecting the addition or the removal of the skip symbol in an alignment process of the received data since the skip symbol is added or is removed to/from the received data after the comma symbol is received.
FIG. 3 is a timing diagram illustrating a conventional method of compensating for a byte skew using only comma symbol. Referring to FIG. 3, a comma symbol COM and three consecutive skip symbols SKPs are transmitted through respective lanes. According to a conventional method of compensating for a byte skew, the comma symbols COMs are synchronously arranged so that the data after the comma symbol COM may be received at the same time. There is no problem in the above method when the data of information to be transferred are received directly after the comma symbol. The skip symbol SKP is, however, received after the comma symbol COM, and the skip symbol SKP is added or removed through an elastic buffer. Therefore, the byte skew may not be compensated for, despite the arrangement based on the comma symbols COMs.
As a result, it is desired to have a method and device which can compensate for the byte skew regardless of an addition or a removal of the skip symbol.